Siddharth A. Ladhake

Low Power Phase Locked Loop with Multiple Output Using Vlsi Technology Siddharth A. Ladhake

DESIGN AND ANALYSIS OF PHASE LOCKED LOOP WITH MULTIPLE OUTPUT USING VLSI TECHNOLOGY Dr. Ujwala A. Belorkar, Dr. Siddharth A. Ladhake. Efforts has been taken to design Low Power, phase locked loop with multiple output, using 45nm VLSI technology. The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirement. When the requirements are not met, the design has to be improved. The proposed PLL is designed and analysed using 45 nm CMOS/VLSI technology with microwind 3.1. The effective gate length required for 45 nm technology is 25nm. Low Power (0.211mwatt) phase locked loop with four multiple outputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz,1.65 GHz, 0.825 GHz, and 0.412 GHz respectively is obtained using 45 nm VLSI technology. Thus a very high efficient, optimum area chip is designed and analysed for phase locked loop with low power of 0.211 mw and four multiple outputs.